This invention relates generally to computer operation during recovery operations, and more particularly to managing PCI Express devices during recovery operations.
Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with peripheral devices via an interface such as the Peripheral Component Interconnect (“PCI”) interface, a local bus standard using parallel data transfer that was developed by Intel Corporation, or the extension of PCI known as PCI-X. More recently, PCI Express, a standard interface incorporating PCI transaction protocols at the logical level, but using serial data transfer at the physical level has been developed to offer better performance than PCI or PCI-X.
Host systems are used in various network applications, including TCP/IP networks, storage area networks (“SANs”), and various types of external device attachment. In SANs, plural storage devices are made available to various host computing systems. Data is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification). The connectivity between a host system and networks or external devices is provided by host bus adapters (“HBAs”), which plug into the host system. HBAs may attach to the host system via a standard interface such as PCI Express.
PCI Express is a low-cost, scalable, switched, point-to-point, serial I/O inter-connection scheme that maintains backward compatibility with PCI. PCI Express provides a number of benefits over existing bus standards, including increased bandwidth availability and support for real-time data transfer services. PCI Express provides quality of service, power management, and I/O virtualization features. Quality of service and power management improve data integrity and allow control of power consumption. I/O virtualization allows data to be routed along logical routes, permits allocation of bandwidth to groups of devices, and provides the ability to prioritize traffic streams.
PCI Express, however, imposes a specific relationship between I/O devices and a PCI Express Root complex. When going through a recovery action in a PCI Express root complex, the attached adapters may have relevant information that is needed for debug purposes. The PCI Express protocol specifies sticky bits in configuration space (typically stored in configuration registers located in the PCI Express adapter) which must stay valid after a reset recovery action. All other memory regions and other pertinent memory space in the adapter may be reset during such actions.
To ensure that this information stays valid for debug purposes while the root complex is being recovered due to an error scenario, the connection needs to appear to remain open. The only known way to do this is described above with respect to the sticky bit schema.